In the field of microelectronics, the constant reduction in the surface area of silicon occupied by the components has up until now made it possible to maintain the race for integration at a rate decreed by Moore's law, which provides that the number of transistors per integrated circuit doubles approximately every 18 to 24 months. However, this race for integration is on the point of coming up against limits of a physical and technological nature that transistors of the metal-oxide-semiconductor (MOS) on solid silicon type will visibly not manage to overcome. Furthermore, architecture on solid silicon will not make it possible to contain, beyond a certain integration threshold, the bidimensional electrostatic forces and certain quantal effects detrimental to the vertical field effect caused by the gate. Current researches in microelectronics are thus exploring novel component architectures, alternative solutions to the conventional MOS transistor. Furthermore, the development of innovative architectures on thin silicon in combination with other so-called “exotic” materials having high mobilities (for example based on carbon, germanium, alloys of elements in group III-V) could make it possible to continue the race towards miniaturisation of components of the CMOS type (the acronym for complementary metal oxide semiconductor).
Devices produced on materials of the semiconductor type other than silicon are usually obtained from epitaxed layers on solid substrates other than silicon (the diameter of which is generally less than or equal to 200 mm). These solid substrates other than silicon have the drawbacks of their cost and their incompatibility in terms of size with equipment developed for the latest generations of silicon components (300 mm, 450 mm in preparation). The use of a solid silicon substrate thus remains the least expensive solution and the most compatible with the known manufacturing methods.
In order to overcome these problems, the method has emerged which consists of obtaining these materials by epitaxial growth on a host silicon substrate of the desired size. However, this approach comes up against the high disparity in lattice parameter between the main materials of interest and silicon. For example, a difference in lattice parameters close to 4% is observed for germanium (Ge) and gallium arsenide (GaAs); this difference is approximately 8% with indium phosphide (InP).
Under these circumstances, obtaining a continuous epitaxial layer (over the entire host substrate), comprising a minimum of crystalline defects, makes it necessary to have recourse to thick intermediate buffer layers, making the approach particularly expensive without being completely effective. This is because there always remains a not insignificant density of dislocations.
By giving up on obtaining a continuous layer, it is possible to achieve lower dislocation densities for heteroepitaxed layers on a silicon substrate. This principle is known by the term “aspect ratio trapping” or “dislocations necking”.
Nevertheless, this approach has several limits. These drawbacks are, for example, illustrated in FIGS. 1a to 1c, coming from the publication by J.-S. Park et al, Applied Physics Letter 90, 052113 (2007). FIG. 1a illustrates a schematic representation of the principle of confinement of dislocations 50 on a layer 300 of germanium formed from a silicon (Si) substrate 100 in a trench 250 formed in a masking layer 200 based on silicon oxide (SiO2). The layer 300 of germanium is grown in the trench 250 formed in a masking layer 200 that covers the silicon substrate 100. By virtue of a minimum aspect ratio, the dislocations 50 are trapped on the flanks and bottom of the layer 300, giving a material better surface quality than the equivalent continuous layer (for the same thickness). As shown in FIG. 1a, the transverse dislocations 50 of the layer 300 of germanium require that the masking layer 200 should have a thickness greater than the width of the trenches 250.
Furthermore, one of the major drawbacks is the emergence of dislocations 50 on a surface that is blocked only in the directions with a high aspect ratio, that is to say in a transverse direction to the trenches 250 (see FIG. 1b illustrating a view in cross section obtained by transmission electron microscopy (TEM)) but not in the length (see FIG. 1c illustrating plan view obtained by transmission electron microscopy (TEM). The dislocations 50 are represented by a more accentuated colour contrast on the TEM images. It can thus be seen that the crystalline defects (or dislocations 50) caused by the growth of the layer 300 from the substrate 100 are located in the bottom of the trench 250, that is to say at the interface with the substrate 100, and along the flanks of the masking layer 200. The strong mismatch in lattice parameter between the substrate 100 and the layer 300 generates defects, more commonly referred to as dislocations, at the interface. The deformation of the crystalline structure in the top layer modifies the angle of inclination of the crystalline planes of said top layer with respect to the crystalline planes of the bottom layer, forming an angle θ.
Moreover, it may be advantageous to grow a constrained material (that is to say one where the lattice parameter in a given direction is different from the relaxed lattice parameter). In this case, there exists a limit referred to as the “critical thickness” beyond which the growth of the material may be accompanied by the creation of crystalline defects and the relaxing of the constraint. If it is wished to produce constrained channels of the “fine” type in a material obtained by vertical growth, the height of the “fine” channels is limited by this “critical thickness”.
In addition, obtaining dense patterns of the layer 300 of germanium is directly limited by the minimum photorepetition pitch. Moreover, an additional drawback lies in the width of the epitaxed channel formed by the layer 300 of germanium that is directly subjected to the variations imposed by the steps of formation of the trenches 250; said trenches 250 being produced by photolithography and/or etching for example.
One object of the present invention thus consists of proposing a method for producing at least one crystalline structure that limits, or even eliminates, at least some of the problems and drawbacks previously mentioned concerning the known solutions of current techniques. More particularly, the objective of the invention is to form a crystalline structure, for example intended to form a transistor channel, from a material other than that of the substrate, devoid of or having few crystalline defects.